This invention relates to a cell transmission phase and rate converting circuit for converting input cell data having an input phase into output cell data having an output phase which is different from the input phase.
A conventional cell transmission phase and rate converting circuit of the type described is for use in an asynchronous transfer mode (ATM) communication system for carrying out transmission and exchange of cells between first and second ATM circuits. The first ATM circuit is operable in accordance with a first clock signal and a first cell phase pulse sequence. The second ATM circuit is operable in accordance with a second clock signal and a second cell phase pulse sequence which are independent of the first clock signal and the first cell phase pulse sequence, respectively. Each of the first and the second cell phase sequences comprises a sequence of cell phase pulses. The first and the second cell phase pulse sequences have first and second periods, respectively. Each of the cells is a packet having a fixed bit length. The first ATM circuit produces, as first cell data, the cells in synchronism with the first clock signal and the first cell phase pulse sequence. The second ATM circuit receives, as second cell data, the cells in synchronism with the second clock signal and the second cell phase pulse sequence. The cell transmission phase and rate converting circuit is connected between the first and the second ATM circuits. The cell transmission phase and rate converting circuit is supplied with the first cell data as the input cell data to produce the second cell data as the output cell data.
More particularly, the cell transmission phase and rate converting circuit is supplied with the first clock signal and the first cell phase pulse sequence by the first ATM circuit as a write-in clock signal and an external write-in pulse sequence, respectively. In addition, the cell transmission phase and rate converting circuit is supplied with the second clock signal and the second cell phase pulse sequence by the second ATM circuit as a read-out clock signal and an external read-out pulse sequence, respectively. The conventional cell transmission phase and rate converting circuit comprises a buffer which is supplied with said input cell data as a write-in cell data and which produces a read-out cell data as the output cell data. The buffer holds the write-in cell data as held cell data to produce the held cell data as the read-out cell data. The conventional cell transmission phase and rate converting circuit further comprises a main control unit for controlling the buffer to write the write-in cell data into the buffer as the held cell data in response to the write-in clock signal and the external write-in pulse sequence and to read the held cell data out of the buffer as the read-out cell data in response to the read-out clock signal and the external read-out pulse sequence.
The conventional cell transmission phase and rate converting circuit is normally operable on the assumption that security is stationarily made as regards all of the write-in clock signal, the external write-in pulse sequence, the read-out clock signal, and the external read-out pulse sequence and the fixed bit length of the cell. Such security is not made in cases, for example, where any miss occurs in any one of the write-in clock signal, the external write-in pulse sequence, the read-out clock signal, and the external read-out pulse sequence by malfunction of the first and/or the second ATM circuits and/or where any pseudo pulse generates by mixing of a noise. Under the circumstances, any phase shift occurs on writing and/or reading of the cells. As a result, the conventional cell transmission phase and rate converting circuit is disadvantageous in that excess data remains in the buffer.
In addition, the remained excess data causes a phase shift between the external read-out pulse sequence and the output cell data. The conventional cell transmission phase and rate converting circuit is defective in that it is impossible to autonomously detect occurrence of such a primary fault.
Another fault, such as an overflow or an underflow, which the control unit does not detect, occurs in the buffer as a secondary fault. In order to correct the secondary fault, it is necessary that the control unit initializes the buffer. Accordingly, the conventional cell transmission phase and rate converting circuit is disadvantageous in that such an initialization causes the buffer to discard other normal cell data and operation of the first and the second ATM circuits stops during the initialization.